Finding the Top-K Heavy Hitters in Data Streams: A Reconfigurable Accelerator Based on an FPGA-Optimized Algorithm

This paper presents a novel approach for accelerating the top-k heavy hitters query in data streams using Field Programmable Gate Arrays (FPGAs). Current hardware acceleration approaches rely on direct and strict mapping of software algorithms into hardware, limiting their performance practicality due to lack optimizations at an algorithmic level. The presented optimizes well-known algorithm by carefully relaxing some its requirements allow design practical scalable accelerator that outperforms current state-of-the-art accelerators while maintaining near-perfect accuracy. details implementation optimized FPGA specifically tailored computing streams. is entirely specified C language level easily reproducible with High-Level Synthesis (HLS) tools. Implementation Intel Arria 10 Stratix FPGAs HLS compiler showed promising results—outperforming prior terms throughput features.